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74ACTQ273 Quiet Series Octal D-Type Flip-Flop
August 1989 Revised August 2001
74ACTQ273 Quiet Series Octal D-Type Flip-Flop
General Description
The ACTQ273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each Dtype input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. The ACTQ utilizes Fairchild Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTO output control and undershoot corrector in addition to a split ground bus for superior performance.
Features
s ICC reduced by 50% s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed pin-to-pin skew AC performance s Improved latch-up immunity s Buffered common clock and asynchronous master reset s Outputs source/sink 24 mA s 4 kV minimum ESD immunity
Ordering Code:
Order Number 74ACTQ273SC 74ACTQ273SJ 74ACTQ273MTC 74ACTQ273PC Package Number M20B M20D MTC20 N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names D0-D7 MR CP Q0-Q7 Description Data Inputs Master Reset Clock Pulse Input Data Outputs
FACT, FACT Quiet Series, and GTO are trademarks of Fairchild Semiconductor Corporation.
(c) 2001 Fairchild Semiconductor Corporation
DS010585
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74ACTQ273
Logic Symbols
IEEE/IEC
Mode Select-Function Table
Inputs Operating Mode MR Reset (Clear) Load "1" Load "0"
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Transition
Outputs Dn X H L Qn L H L
CP
L H H

X
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74ACTQ273
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI = -0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = -0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) DC Latch-up Source or Sink Current Junction Temperature (TJ) PDIP 140C
-0.5V to +7.0V -20 mA +20 mA -0.5V to VCC + 0.5V -20 mA +20 mA -0.5V to VCC + 0.5V 50 mA 50 mA -65C to +150C 300 mA
Recommended Operating Conditions
Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate V/t VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 125 mV/ns 4.5V to 5.5V 0V to VCC 0V to VCC
-40C to +85C
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics
Symbol VIH VIL VOH Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage V CC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum LOW Level Output Voltage 4.5 5.5 4.5 5.5 IIN ICCT IOLD IOHD ICC VOLP VOLV VIHD VILD Maximum Input Leakage Current Maximum ICC/Input Minimum Dynamic Output Current (Note 3) Maximum Quiescent Supply Current Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage 5.5 5.5 5.5 5.5 5.5 5.0 5.0 5.0 5.0 1.1 -0.6 1.9 1.2 4.0 1.5 -1.2 2.2 0.8 0.6 0.001 0.001 TA = +25C Typ 1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.1 0.1 0.36 0.36 0.1 TA = -40C to +85C Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 1.0 1.5 75 -75 40.0 A mA mA mA A V V V V V Units V V V Conditions VOUT = 0.1V or VCC - 0.1V VOUT = 0.1V or VCC - 0.1V IOUT = -50 A VIN = VIL or VIH V IOH = -24 mA IOH = -24 mA (Note 2) IOUT = 50 A VIN = VIL or VIH V IOL = 24 mA IOL = 24 mA (Note 2) VI = VCC, GND VI = VCC - 2.1V VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND Figures 1, 2 (Note 4) Figures 1, 2 (Note 4) (Note 5) (Note 5)
Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: Max number of outputs defined as (n). n - 1 Data inputs are driven 0V to 3V; one output @ GND. Note 5: Max number of Data Inputs (n) switching. (n - 1) Inputs switching 0V to 3V (ACTQ). Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD) f = 1 MHz.
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74ACTQ273
AC Electrical Characteristics
VCC Symbol Parameter (V) (Note 6) fMAX tPLH tPHL tPHL tOSHL, tOSLH Maximum Clock Frequency Propagation Delay CP to Qn Propagation Delay MR to Qn Output to Output Skew (Note 7) 5.0 5.0 5.0 5.0 Min 125 1.5 1.5 TA = +25C CL = 50 pF Typ 189 6.5 7.0 0.5 8.5 9.0 1.0 Max TA = -40C to +85C CL = 50 pF Min 110 1.5 1.5 9.0 9.5 1.0 Max MHz ns ns ns Units
Note 6: Voltage Range 5.0 is 5.0V 0.5V Note 7: Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs within the same packaged device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. Not tested.
AC Operating Requirements
VCC Symbol Parameter (V) (Note 8) tS tH tW Setup Time, HIGH or LOW Dn to CP Hold Time, HIGH or LOW Dn to CP Clock Pulse Width HIGH or LOW tW tW MR Pulse Width HIGH or LOW Recovery Time MR to CP
Note 8: Voltage Range 5.0 is 5.0V 0.5V
TA = +25C CL = 50 pF Typ 1.0 -0.5 2.0 3.5 1.5 4.0
TA = -40C to +85C CL = 50 pF Guaranteed Minimum 3.5 1.5 4.0 ns ns ns Units
5.0 5.0 5.0
5.0 5.0
1.5 0.5
4.0 3.0
4.0 3.0
ns ns
Capacitance
Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 4.5 40.0 Units pF pF VCC = OPEN VCC = 5.0V Conditions
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74ACTQ273
FACT Noise Characteristics
The setup of a noise characteristics measurement is critical to the accuracy and repeatability of the tests. The following is a brief description of the setup used to measure the noise characteristics of FACT. Equipment: Hewlett Packard Model 8180A Word Generator PC-163A Test Fixture Tektronics Model 7854 Oscilloscope Procedure: 1. Verify Test Fixture Loading: Standard Load 50 pF, 500. 2. Deskew the HFS generator so that no two channels have greater than 150 ps skew between them. This requires that the oscilloscope be deskewed first. It is important to deskew the HFS generator channels before testing. This will ensure that the outputs switch simultaneously. 3. Terminate all inputs and outputs to ensure proper loading of the outputs and that the input levels are at the correct voltage. 4. Set the HFS generator to toggle all but one output at a frequency of 1 MHz. Greater frequencies will increase DUT heating and effect the results of the measurement. 5. Set the HFS generator input levels at 0V LOW and 3V HIGH for ACT devices and 0V LOW and 5V HIGH for AC devices. Verify levels with an oscilloscope. VOLP/VOLV and VOHP/V OHV: * Determine the quiet output pin that demonstrates the greatest noise levels. The worst case pin will usually be the furthest from the ground pin. Monitor the output voltages using a 50 coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. * Measure VOLP and VOLV on the quiet output during the worst case transition for active and enable. Measure VOHP and VOHV on the quiet output during the worst case active and enable transition. * Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements. VILD and VIHD: * Monitor one of the switching outputs using a 50 coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. * First increase the input LOW voltage level, VIL, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input LOW voltage level at which oscillation occurs is defined as VILD. * Next decrease the input HIGH voltage level, VIH, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input HIGH voltage level at which oscillation occurs is defined as VIHD. * Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements.
FIGURE 1. Quiet Output Noise Voltage Waveforms
Note 9: VOHV and VOLP are measured with respect to ground reference. Note 10: Input pulses have the following characteristics: f = 1 MHz, tr = 3 ns, tf = 3 ns, skew < 150 ps.
FIGURE 2. Simultaneous Switching Test Circuit
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74ACTQ273
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B
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74ACTQ273
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D
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74ACTQ273
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20
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74ACTQ273 Quiet Series Octal D-Type Flip-Flop
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 9 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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